module fifo_control(

	input		wire					clk,
	input		wire					ret_n,
	input		wire					empty,
	input		wire					full,
	
	output	reg					rd_en,
	output	reg					wr_en

); 
	
	parameter cnt_max_time = 20'd100_000;
	
	reg	[19:0]	cnt_time;

	
	always @(posedge clk or negedge ret_n)
		if(!ret_n)
			wr_en <= 1'b0;
		else if(empty)
			wr_en <= 1'b1;
		else if(full)
			wr_en <= 1'b0;
		else 
			wr_en <= wr_en;

	
	always @(posedge clk or negedge ret_n)
		if(!ret_n)
			cnt_time <= 20'd0;
		else if(cnt_time >= cnt_max_time)
			cnt_time <= 20'd0;
		else 
			cnt_time <= cnt_time + 1'b1;
			
	always @(posedge clk or negedge ret_n)
		if(!ret_n)
			rd_en <= 1'b0;
		else if(cnt_time == 20'd5)
			rd_en <= 1'b1;
		else 
			rd_en <= 1'b0;
			
	
















endmodule 